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| Ver2.0 A1 PROs AI325CA 1/3 inch CCD Image Sensor for NTSC Camera GENERAL DESCRIPTION The AI325CA is a 250K pixels CCD area sensor for NTSC 1/3 inch video cameras. Buried photodiodes and micro lenses are adopted for low noise, low smear and high sensitivity. A chrominance signal is achieved by the adoption of Yellow, Magenta, Cyan and Green complementary color mosaic filters. This product also has the features of strong antiblooming and electronic shutter with variable charge-storage time. 16 Pin Plastic - DIP ( Top View ) V V V 4 3 2 1 2 3 16 H 15 H 2 1 V1 4 GND 5 VNC 6 GG NC VSS 7 VOUT 8 14 NC 13 V VRG RG 12 VP 11 VSUB 10 GND 9 VDD FEATURES * Micro lens arrays for high sensitivity * Ye, Mg, Cy and G complementary color mosaic filters * Excellent blooming suppression * TTL level(5V) operation on HCCD & RG electrodes * 16 pin plastic DIP type package * Variable electronic shutter of 1/60 to 1/100,000 sec * High sensitivity and low smear * Low image lag STRUCTURE Optical black position ( Top View ) * Architecture : IT - CCD * Optical size : 1/3 inch format * Chip size : 6.0(H) x 5.2(V) * Number of effective pixels : 510 (H) x 492 (V) about 250K pixels * Number of total pixels : 537 (H) x 505 (V) about 270K pixels * Pixel size : 9.65 (H) x 7.5 (V) 2 * Optical black area Horizontal direction : Front 2 pixels Rear 25 pixels Vertical direction : Front 12 pixels Rear 1 pixels * Number of dummy bits Horizontal : 16 Vertical : 1 ( Even field only ) Pin1 1 Unit : Pixels 492 12 2 Pin9 510 25 1 AI325CA BLOCK DIAGRAM VOUT 8 NC 7 NC 6 GND 5 V 4 1 V 3 2 V 2 3 V 1 4 PD VCCD HCCD 9 10 11 12 13 14 15 16 VDD GND VSUB VP VRG NC H 1 H 2 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Symbol V V V V 4 3 2 1 Description Vertical register transfer clock 4 Vertical register transfer clock 3 Vertical register transfer clock 2 Vertical register transfer clock 1 Ground No connection No connection CCD output signal Pin 9 10 11 12 13 14 15 16 Symbol VDD GND VSUB VP VRG NC H H 1 2 Description Output amplifier drain bias Ground Substrate (Overflow drain) bias Protection bias Reset gate clock No connection Horizontal register transfer clock 1 Horizontal register transfer clock 2 GND NC NC VOUT ABSOLUTE MAXIMUM RATINGS Parameter Substrate voltage Supply voltage Symbol VSUB - GND VDD, VOUT - GND VDD, VOUT - VSUB V 1, 2, 3, 4 - GND V 1, 2, 3, 4 - VP V 1, 2, 3, 4 - VSUB H 1, Value -0.3 to +55 -0.3 to +18 -55 to +10 -10 to +20 -0.3 to +27 -55 to +10 -10 to +15 -10 to +15 4 Unit V V V V V V V V V V V V C C Vertical clock input voltage Horizontal clock input voltage Between vertical clock input pins Between horizontal clock and vertical clock input pins Output pin voltage Protective circuit voltage Storage temperature Operation temperature H X 2 - GND Y V H 1, -V 2 H -V -17 to +17 -10 to +15 -55 to +10 -65 to 0.3 -30 to 80 -10 to 60 RG - GND RG - VSUB VP - VSUB TSTG TOPR * Protective circuit voltage(VP) is induced to the image sensor before VDD supplied power voltage. 2 AI325CA BIAS CONDITION Parameter Output amplifier drain voltage Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate voltage adjustment Protection bias Symbol VDD VSUB VSUB VRG VRG VP Min 14.5 5 -1 0 -3 Typ 15.0 Max 15.5 15 1 4 3 Unit V V V V % Remark * Set to low level of vertical transfer clock * No adjustment of reset gate clock voltage is necessary when reset gate clock is driven as indicated below. Parameter Reset gate clock voltage VRG 8.5 9.0 9.5 V Symbol VRGL Min -0.2 Typ 0.0 Max 0.2 Unit V Remarks DC CHARACTERISTICS Parameter Output amplifier drain current Symbol IDD Min - Typ 3 Max - Unit DRIVING CONDITION Parameter Vertical clock high voltage Vertical clock middle voltage Vertical clock low voltage Horizontal clock high voltage Horizontal clock low voltage RG clock voltage difference Substrate clock voltage Symbol VH1, VH3 VM1, 2, 3, 4 VL1, 2, 3, 4 HH1, 2 HL1, 2 RGHL VSUB Min 14.5 -0.2 -9.0 4.5 -0.5 4.7 23 Typ 15.0 0.0 -8.5 5.0 0.0 5.0 24 Max 15.5 0.2 -8.0 5.5 0.5 5.3 25 Unit V V V V V V V 3 AI325CA ELECTRO-OPTICAL PERFORMANCE ( Ta = 25 C ) Item Sensitivity Saturation signal Smear Blooming Video signal shading Uniformity between video signal channels Dark signal level Dark signal shading Flicker Y Flicker B-Y, R-Y Line crawl R, G, B, W Image lagging Symbol SENS VSAT SMR BL OSNU Sr Sb VDARK DSNU FY FCr, FCb LCr, LCb, LCg, LCw Lag Min 65 900 Typ 80 Max Unit mV/Lux mV Measurement Method 1 2 3 4 7 9 9 6 8 5 10 11 12 Remark Temp=60 C 0.015 1 25 10 10 2 2 2 5 20 0.5 % % % % % mV mV % % % % Temp=60 C Temp=60 C 4 AI325CA MESUREMENT METHOD 1. Sensitivity Set to SILC ( Standard Illumination Conditions* ) Measure the average value of signal output ( VOUT ) Calculate the efficiency of VOUT to light intensity 2. VSAT Adjust light intensity to 200 times of SILC Measure the average value of signal output 3. Smear Adjust light intensity to 200 times of SILC & readout clock Measure the signal output at horizontal optical black ( VHOPB ) Measure the signal output at vertical blanking dummy ( VVBD ) Smear = { (VVBD - VHOPB) / VSAT } 100 ( % ) 4. Blooming Adjust light intensity to 200 times of SILC & readout clock Measure the signal output at horizontal optical black (VHOPB ) Measure the signal output at blooming dummy area ( VBD ) Blooming = { ( VBD - VHOPB ) / VSAT } 100 ( % ) 5. OSNU Set to SILC Measure the average value of signal output ( VOUT ) Measure the maximum value and the minimum value of signal output OSNU = ( VMAX - VMIN ) / VOUT 100 (%) 6. Sr, Sb Set to SILC Measure the average value of signal output ( VOUT ) Measure the maximum value and minimum value of chroma output Sr = ( CrMAX - CrMIN ) / VOUT 100 (%) Sb= ( CbMAX - CbMIN ) / VOUT 100 (%) 7. VDARK Measure the average value of signal output at dark condition 8. DSNU Measure the voltage difference between minimum and maximum of dark signal 5 AI325CA 9. FY Set to SILC Measure the average value of signal output ( VOUT ) Measure the difference of signal output between even field and odd field FLK = ( VOUT/ VOUT ) 100 (%) 10. FCr, FCb Set to SILC using the R,B optical filter respectively Measure the average value of chroma signal output Measure the difference of chroma signal output between even field and odd field FCi = ( VCiOUT / VCiOUT ) 100 (%) ( i = r,b ) 11. LCr, LCb, LCg, LCw Set to SILC using the W,R,B,G optical filter respectively Measure the average value of signal output Measure the difference of signal output between signal lines of the same field ( Vlw, Vlr, Vlg, Vlb) Lci = ( VliOUT / ViOUT ) 100 (%) ( i = w,r,g,b ) 12. Lag Light a strobe lamp as follow TG V1 odd V2 even V3 odd V4 even Str Lag = { V2(out)+V3(out)+V4(out) } / V1(out) * Standard Illumination Conditions Measure the average value of output of linear region At this time, measure the light intensity of illumination at CCD face plate Define SILC with above Light source: Tungsten lamp(3100K) Use a standard test lens at F8 6 AI325CA +15V 100 C2223 1M 100 9 VDD 10 GND 11 -9V RG 12 VSUB VP 13 VRG 33 14 NC 8 VOUT NC NC GND 7 6 5 KDS226 VR 10K 3.3K CCD output 3.9K 0.1 V-DRIVER Ai1002(3) VSUB AI325CA V V 15 H V 1 4 2 V 3 2 1 V 2 APPLICATION CIRCUIT H H 1 33 2 1 3 V 16 H 33 V 2 3 4 1 V 4 7 AI325CA PACKAGE DIMENSION (16 PIN PLASTIC-DIP) B 6.1 UNIT = mm 1.The center of the effective image area relative to " B " and " B' "is (H, V) = (6.1, 5.7) 0.15mm. R0 DE .5 PT H= 0.4 V 2. The rotation angle of the effective image area relative to H and V is 1.5 H B : GLASS LID 5.7 2.5 0.10 R 0.3 0.3 12.20 8.9 0.1 3 0.3 11.40 9.70 0.1 0.10 0.32 1.57 0.64 0.10 5 0.25 3.08 1.40 0.10 5 10.73 0.05 R0.3 0.30 0.46 1.27 0.10 0.10 1.27 11.80 0.05 0.10 0.05 1.27X7=8.89 3.55 0.25 11.43 0.3 8 |
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